State Decoder

The STATE decoder interprets the data as a clocked bus with enable and framing controls. It samples the data on each specified clock edge and displays the results. The data is displayed in HEX, Decimal, ASCII, Octal or Binary. The channels do not need to be consecutive. We abstract a single value from only the selected channels.

The STATE decoder is one of many signal decoders included with all DigiView Logic Analyzers.

State overview

The DigiView software provides extensive navigation, search, measurement, export, plot and printing capabilities to all signal types. The STATE Decoder adds STATE specific decoding and configuration options.

Demo Video
Frame Sync Options:
  • Sync on Rising Edge
  • Sync on Falling Edge
  • Sync on Rising or Falling Edge
  • Sync on Rising and End on Falling
  • Sync on Falling and End on Rising
Configuration options include:
  • Clock on rising, falling or DDR clock edges
  • Supports Enable and Frame Sync Signals
  • Enable on High or Low Edge
  • Ignore Enable and Frame Sync
  • Invert Data Channels
  • Frame Length Specifier (# of States)
  • Framing Timeout Specifier (or Ignore)
Help Video
STATE Decoder
State Decoder

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